Efficient Procedures for Minimizing the Standby Power in Dual VT CMOS Circuits

In this paper we present efficient procedures for delay constrained minimization of the power due to leakage in CMOS digital circuits for a dual threshold voltage (VT ) technology. The availability of two or more threshold voltages on the same chip provides a new opportunity for circuit designers to make tradeoffs between power and delay. We present two efficient procedures that take as input a gate level netlist and assign the proper threshold voltage to each transistor so that the leakage power is minimized but without violating the delay constraints. Experimental results on the MCNC91 benchmark circuits show that up to one order of magnitude power reduction can be achieved without any delay increase when compared to a circuit where all transistors are low VT devices.